The present invention relates generally to pipeline computers having store buffers for temporary storage of a store request, and more particularly to a technique for reducing the waiting time of a load request that occurs immediately following a store request for transaction data from an arithmetic logic unit.
In pipeline computers, each execution instruction is divided into sub-instructions which are executed serially with those of another instruction in order to reduce execution time. In a pipeline computer, a set of buffers known as "store" buffers are used in addition to cache memories as a means for temporary storage of address and transaction data associated with a "store" request, or sub-instruction before storing it into the main memory. The information stored in the main memory is then retrieved in response to a "load" request (sub-instruction) into the internal storage of the computer such as buffers and registers. The reasons for the provision of store buffers are (1) to accommodate timing differences between store request address and store request transaction data and (2) to put "store" requests in a queue when a conflict arises with a higher priority "load" request until the latter is executed except when a need aries for transaction data associated with a store sub-instruction of which the subsequent load sub-instruction is not yet executed otherwise the prior execution of a later load sub-instruction will cause old transaction data to be returned to the request source. Under such circumstances, all unexecuted store sub-instructions in store buffers are stored into the main memory first and then the subsequent load sub-instruction is executed. In this way, data conflicts between different instructions are avoided. Since a substantial amount of time is required to execute all of the pending "store sub-instructions" and then execute a subsequent load sub-instruction, the request source must wait in a long queue for desired data.